free web design templates

## UNIVERSITY OF NOTTINGHAM OPEN BERT - An Open Source Bit Error Rate Tester

### Authors: Michael Basford, Angel Pena-Quintal

Motivation

This Open Source project started as way of proposing solutions in the field of wired communications and the validation of Bit Error Rate Testers under Electromagnetic Emissions. It is well-known that this type of high-end equipment can be expensive. For this reason the authors decided to address the very basic theory for measuring BER in this Open Source Project.

In this project you will find.

The verilog code and modules used for the BER tester.

The user interphase software for the RS-232 serial communication terminal.

The Schematic of the BER tester.

The PCB layout.

For this project, we will need two softwares.

1. Quartus Prime. To create the HDL modules and the soft CPU.
2. Nios II.  To create the serial interface for the soft cpu.

https://fpgasoftware.intel.com/?edition=lite

Theory

Fundamentally, a BERT must ﬁnd the ratio of incorrectly transmitted bits to transmitted bits, as given by the next equation.

$\text{BER} = \frac{N_{err}}{B_{bits}}$

where $$N_{err}$$ is the number of incorrect bits whilst $$N_{bits}$$ is  the total number of bits sent in a time period. When data is transmitted over a data link, there is a possibility of bit errors being introduced into the system.

The main Integrated Circuit of the project is an Intel FPGA Cyclone  IV. This FPGA permits the parallelisation of processes within the same device, ensuring that absolute-time dependant operations may happen repeatably and without unexpected interruptions, as might be expected from the use of a microcontroller.

The fundamental BERT processes of random bit generation, transmission and comparison are handled within the module marked BERT. To permit the adjustment of data throughput, the BERT module is fed a clock sourced from a frequency divider, controlled by the soft-CPU. This is itself fed by the Phase-Locked-Loop (PLL) module which takes the 48 MHz input clock and multiplies it to 320 MHz output clock allowing for the generation of data at speed far exceeding that which a purely CPU-based system would allow.

Schematic

As was mentioned before, the BER testers uses FPGA Cyclone IV, in this case the EP4CE10E22C8. This FPGA can be purchased on online stores such as Farnell and Digikey. Moreover, there exists a development board based on this exact FPGA.

Regarding the PCB development. We would like to address some of the more interesting points.

- The use of a DB9 for serial communications.

- The use of high speed comparators for the data input.

- The use TTL/Cmos output buffer frequency to achieve 600 MHz with less than 200 ps output pulse skew. In addition, all outputs match 50 ohm transmission line impedance.

The Schematic can be seen in the next figure. Feel free to take the design to modify as you like.

Schematic

PCB

The PCB is one the more interesting parts of this project. The design of this PCB has been done using Altium Designer.

The next figure shows the top layer.

PCB Top Layer Designed in Altium Designer

PCB Bottom Layer Designed in Altium Designer

PCB Design

NIOS II Code and Serial communication.

Finally, the project will find its usage when NIOS II software is linked with the soft cpu of the FPGA module. The code can be downloaded in the next link. It is worth mentioning that the code can be modified due to the fact that is C based. Feel free to improve and use the code to apply for your aims.

NIOS Code

Finally

The whole project can be downloaded in the next link. In this folder you will find the Quartus Prime files.

Quartus Prime Design Files

This blog will be updated with projects and improvements for the Open Source BERt.

Special thanks to the George Green Instutite for Electromagnetic Research (GGIEMR) of The University of Nottingham to support the development of the project.

Have a look to the website:

GGIEMR